US 11,817,157 B2
Systems and methods for detecting erratic programming in a memory system
Ming Wang, Shanghai (CN); Liang Li, Shanghai (CN); and Shih-Chung Lee, Yokohama (JP)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 14, 2021, as Appl. No. 17/346,880.
Claims priority of application No. 202110618598.0 (CN), filed on Jun. 3, 2021.
Prior Publication US 2022/0392553 A1, Dec. 8, 2022
Int. Cl. G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a non-volatile memory including a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines, wherein the control circuitry is configured to program the memory cells of the plurality of word lines in a plurality of programming loops, the programming loops including:
applying a programming pulse to a selected word line of the plurality of word lines;
applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells being programmed to a data state N−1, wherein the data state N−1 corresponds to a data state having a threshold voltage range lower than a threshold voltage range corresponding to the data state N; and
inhibiting further programming of the memory cells already having been programmed to data state N in response to the verify of the lower tail of data state N passing, and to incrementally advance the data states being verified by incrementing N to N+1 (N=N+1).