US 11,817,156 B2
Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Jan. 19, 2022, as Appl. No. 17/579,364.
Application 17/579,364 is a division of application No. 16/901,758, filed on Jun. 15, 2020, granted, now 11,270,779.
Application 16/901,758 is a continuation of application No. 15/820,337, filed on Nov. 21, 2017, granted, now 10,741,264, issued on Aug. 11, 2020.
Application 15/820,337 is a continuation of application No. 15/220,375, filed on Jul. 26, 2016, granted, now 9,892,800, issued on Feb. 13, 2018.
Claims priority of provisional application 62/235,322, filed on Sep. 30, 2015.
Prior Publication US 2022/0139472 A1, May 5, 2022
Int. Cl. G11C 16/34 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/28 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/792 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); G11C 11/56 (2006.01); H10B 43/10 (2023.01)
CPC G11C 16/3431 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0416 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/0491 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01); H01L 27/0688 (2013.01); H01L 29/40117 (2019.08); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H05K 999/99 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 43/10 (2023.02)] 32 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a semiconductor substrate having a substantially planar surface and having circuitry formed therein and thereon;
an insulating layer over the semiconductor substrate;
a first stack of active strips and a second stack of active strips formed over the insulating layer and directly above the circuitry of the semiconductor substrate, wherein:
(i) each stack of active strips comprises two or more active strips provided one on top of another and electrically isolated from each other, the active strips (a) being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, and each comprising a semiconductor layer provided between a first conductive layer and a second conductive layer; and
(ii) the first stack and the second stack being separated from each other a predetermined distance along a second direction transverse to the first direction and parallel to the planar surface;
a data storage material provided on sidewalls of the first and second stacks;
a plurality of local conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each local conductor being separated from one or both of the first and the second stacks by the data storage material; and
first global conductive wiring having conductors each running along the second direction for connecting the local conductors to the circuitry;
wherein each active strip further comprises a pre-charge transistor that is formed out of the semiconductor layer, the first and the second conductive layers of the active strip and a designated one of the local conductors that is adjacent to the active strip.