US 11,817,152 B2
Generating embedded data in memory cells in a memory sub-system
Bruce A. Liikanen, Berthoud, CO (US); Michael Sheperek, Longmont, CO (US); and Larry J. Koudele, Erie, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 22, 2022, as Appl. No. 17/892,721.
Application 17/892,721 is a continuation of application No. 17/086,964, filed on Nov. 2, 2020, granted, now 11,423,989.
Prior Publication US 2022/0406381 A1, Dec. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/10 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0638 (2013.01); G06F 3/0679 (2013.01); G11C 16/26 (2013.01); G11C 11/56 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
determining a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution level corresponding to the memory cells of the memory sub-system;
selecting an offset voltage level corresponding to the point at the target bit error rate;
programming a first portion of a first group of the memory cells in the first programming voltage distribution level at a threshold voltage level to set a first embedded data value; and
programming a second portion of a second group of the memory cells in the second programming voltage distribution level at the threshold voltage level offset by the offset voltage level to set a second embedded data value.