CPC G11C 14/0063 (2013.01) | 20 Claims |
1. An integrated circuit comprising:
a memory device comprising a plurality of memory points, each memory point comprising a volatile memory cell and a single non-volatile memory cell; and
a power device comprising:
a main power stage configured to supply a first power voltage for operating the memory device; and
a secondary power stage configured to supply a second power voltage for powering a write operation of the non-volatile memory cells in response to a shutdown of the memory device, the secondary power stage comprising:
a first charge pump circuit configured to generate the second power voltage from the first power voltage, wherein the second power voltage is greater than the first power voltage;
a capacitor switchably coupled to the first charge pump circuit, and configured to be charged at the second power voltage; and
a second charge pump circuit switchably coupled to the capacitor, and comprising a plurality of elementary charge pump stages switchably coupled in a series.
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