US 11,817,149 B2
Non volatile static random access memory device and corresponding control method
François Tailliet, Fuveau (FR); and Marc Battista, Allauch (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Sep. 7, 2022, as Appl. No. 17/930,250.
Application 17/930,250 is a continuation of application No. 17/157,631, filed on Jan. 25, 2021, granted, now 11,488,666.
Prior Publication US 2023/0005540 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 14/00 (2006.01)
CPC G11C 14/0063 (2013.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a memory device comprising a plurality of memory points, each memory point comprising a volatile memory cell and a single non-volatile memory cell; and
a power device comprising:
a main power stage configured to supply a first power voltage for operating the memory device; and
a secondary power stage configured to supply a second power voltage for powering a write operation of the non-volatile memory cells in response to a shutdown of the memory device, the secondary power stage comprising:
a first charge pump circuit configured to generate the second power voltage from the first power voltage, wherein the second power voltage is greater than the first power voltage;
a capacitor switchably coupled to the first charge pump circuit, and configured to be charged at the second power voltage; and
a second charge pump circuit switchably coupled to the capacitor, and comprising a plurality of elementary charge pump stages switchably coupled in a series.