US 11,816,563 B2
Method of enabling sparse neural networks on memresistive accelerators
Titash Rakshit, Austin, TX (US); Ryan M. Hatcher, Austin, TX (US); Jorge A. Kittl, Austin, TX (US); Borna J. Obradovic, Leander, TX (US); and Engin Ipek, Pittsford, NY (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 10, 2019, as Appl. No. 16/409,487.
Claims priority of provisional application 62/793,731, filed on Jan. 17, 2019.
Prior Publication US 2020/0234114 A1, Jul. 23, 2020
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06N 3/08 (2023.01); G06F 17/16 (2006.01)
CPC G06N 3/08 (2013.01) [G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of storing a sparse weight matrix for a trained artificial neural network in a circuit comprising a plurality of clusters, the method comprising:
partitioning the sparse weight matrix, based on an arrangement of zero-value weights and non-zero value weights in the sparse weight matrix, into at least one first sub-block and at least one second sub-block, the at least one first sub-block comprising a plurality of weight values, the plurality of weight values of the at least one first sub-block containing only zero-value weights and the at least one second sub-block comprising non-zero value weights; and
assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the plurality of clusters of the circuit,
wherein the circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector.