US 11,816,505 B2
Configurable logic platform with reconfigurable processing circuitry
Mark Henrik Sandstrom, Alexandria, VA (US)
Assigned to ThroughPuter, Inc., Williamsburg, VA (US)
Filed by ThroughPuter, Inc., Williamsburg, VA (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,526.
Application 17/979,526 is a continuation of application No. 17/859,657, filed on Jul. 7, 2022, granted, now 11,500,682.
Application 17/859,657 is a continuation of application No. 17/470,926, filed on Sep. 9, 2021, granted, now 11,385,934, issued on Jul. 12, 2022.
Application 17/470,926 is a continuation of application No. 17/463,098, filed on Aug. 31, 2021, granted, now 11,347,556, issued on May 31, 2022.
Application 17/463,098 is a continuation of application No. 17/344,636, filed on Jun. 10, 2021, granted, now 11,188,388, issued on Nov. 30, 2021.
Application 17/344,636 is a continuation of application No. 17/195,174, filed on Mar. 8, 2021, granted, now 11,036,556, issued on Jun. 15, 2021.
Application 17/195,174 is a continuation of application No. 16/434,581, filed on Jun. 7, 2019, granted, now 10,942,778, issued on Mar. 9, 2021.
Application 16/434,581 is a continuation of application No. 15/267,153, filed on Sep. 16, 2016, granted, now 10,318,353, issued on Jun. 11, 2019.
Application 15/267,153 is a continuation of application No. 14/318,512, filed on Jun. 27, 2014, granted, now 9,448,847, issued on Sep. 20, 2016.
Claims priority of provisional application 61/934,747, filed on Feb. 1, 2014.
Claims priority of provisional application 61/869,646, filed on Aug. 23, 2013.
Prior Publication US 2023/0053365 A1, Feb. 23, 2023
Int. Cl. G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 8/656 (2018.01); G06F 15/80 (2006.01); H04L 47/78 (2022.01); G06F 15/173 (2006.01)
CPC G06F 9/5038 (2013.01) [G06F 9/4881 (2013.01); G06F 8/656 (2018.02); G06F 9/5027 (2013.01); G06F 15/173 (2013.01); G06F 15/80 (2013.01); G06F 2209/483 (2013.01); G06F 2209/5021 (2013.01); H04L 47/78 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A parallel data processing platform comprising:
a plurality of programmable logic-based processing units, each comprising
at least one input port to receive data packets,
a plurality of reconfigurable processing cores, separately configurable to perform respective processing tasks, wherein in at least a first configuration, a first processing core of the plurality of reconfigurable processing cores is configured to instantiate a first task, and a second processing core of the plurality of reconfigurable processing cores is configured to instantiate a second task, different than the first task,
a hardware-configured set of task-specific packet buffers,
a hardware-configured demultiplexer to demultiplex data packets received at the at least one input port into corresponding ones of the task-specific packet buffers, in dependence on a respective value of at least one identifier included in each received data packet, and
multiplexing logic to, for each respective packet buffer of the task-specific packet buffers, direct data packets from the respective packet buffer to a corresponding one of the plurality of reconfigurable processing cores that is in a current task configuration corresponding to the respective packet buffer.