CPC G06F 9/5038 (2013.01) [G06F 9/4881 (2013.01); G06F 8/656 (2018.02); G06F 9/5027 (2013.01); G06F 15/173 (2013.01); G06F 15/80 (2013.01); G06F 2209/483 (2013.01); G06F 2209/5021 (2013.01); H04L 47/78 (2013.01)] | 17 Claims |
1. A parallel data processing platform comprising:
a plurality of programmable logic-based processing units, each comprising
at least one input port to receive data packets,
a plurality of reconfigurable processing cores, separately configurable to perform respective processing tasks, wherein in at least a first configuration, a first processing core of the plurality of reconfigurable processing cores is configured to instantiate a first task, and a second processing core of the plurality of reconfigurable processing cores is configured to instantiate a second task, different than the first task,
a hardware-configured set of task-specific packet buffers,
a hardware-configured demultiplexer to demultiplex data packets received at the at least one input port into corresponding ones of the task-specific packet buffers, in dependence on a respective value of at least one identifier included in each received data packet, and
multiplexing logic to, for each respective packet buffer of the task-specific packet buffers, direct data packets from the respective packet buffer to a corresponding one of the plurality of reconfigurable processing cores that is in a current task configuration corresponding to the respective packet buffer.
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