CPC G06F 30/327 (2020.01) [G06F 13/1673 (2013.01); G06F 30/3312 (2020.01)] | 18 Claims |
1. A computer-implemented method for synthesizing a digital circuit, comprising:
receiving a multi-threaded software program with at least one C++ thread;
generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and
automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.
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