CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 16/3459 (2013.01)] | 20 Claims |
1. An apparatus comprising:
one or more control circuits configured to control a memory structure that comprises non-volatile memory cells, wherein the one or more control circuits are configured to:
program data into respective groups of the non-volatile memory cells;
accumulate parity for the data in response to the data being programmed into the respective groups, wherein the accumulated parity is based on the data programmed into each respective group;
perform a post-program read test of each respective group after programming the data into the respective groups;
responsive to a determination that the post-program read test failed for a group of the non-volatile memory cells, re-calculate the parity such that the parity is based on data stored in the groups that passed the post-program read test but not the data stored in the group that failed the post-program read test; and
program the re-calculated parity to a group of the non-volatile memory cells other than the respective groups.
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