US 11,816,339 B2
Selectable error control for memory device
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 2, 2021, as Appl. No. 17/391,898.
Claims priority of provisional application 63/075,290, filed on Sep. 7, 2020.
Prior Publication US 2022/0075532 A1, Mar. 10, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 35 Claims
OG exemplary drawing
 
11. A method, comprising:
identifying, at a memory device, that a value stored at a register indicates a first error control operation for applying to data stored in a memory array of the memory device from a set of error control operations that includes the first error control operation and a second error control operation;
activating a first plurality of gates configured to generate a first set of bits associated with a first matrix of the first error control operation based at least in part on identifying that the value indicates the first error control operation;
deactivating a second plurality of gates configured to generate a second set of bits associated with a second matrix of the second error control operation based at least in part on identifying the value stored at the register; and
generating the first set of bits at the first plurality of gates and a third plurality of gates based at least in part on activating the first plurality of gates, wherein the third plurality of gates is associated with the first matrix and the second matrix.