CPC G06F 13/1689 (2013.01) [G06F 12/00 (2013.01); G11C 7/10 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 2207/2254 (2013.01)] | 21 Claims |
1. A memory controller to a control a memory device, the memory controller comprising:
circuitry to identify an event where the memory device has not transferred data for a least a predetermined idle period;
circuitry to cause, in response to the event, the memory device to commence outputting of a specified timing reference signal prior to transfer of data following passage of the predetermined idle period;
circuitry to calibrate a value of a timing parameter in the memory controller using the specified timing reference signal; and
circuitry to receive the data transferred from the memory device following passage of the predetermined idle period in dependence on the calibrated value of the timing parameter.
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