US 11,816,040 B2
Device memory protection for supporting trust domains
Vidhya Krishnan, Folsom, CA (US); Siddhartha Chhabra, Portland, OR (US); David Puffer, Tempe, AZ (US); Ankur Shah, Folsom, CA (US); Daniel Nemiroff, El Dorado Hills, CA (US); and Utkarsh Y. Kakaiya, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 2, 2022, as Appl. No. 17/712,109.
Prior Publication US 2022/0222185 A1, Jul. 14, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/1433 (2013.01) [G06F 11/1004 (2013.01); G06F 12/0292 (2013.01); G06F 12/1408 (2013.01); G06F 12/1466 (2013.01); G06F 12/1483 (2013.01)] 21 Claims
OG exemplary drawing
 
1. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
allocating device memory in a system, allocating the device memory including allocating memory for one or more trust domains (TDs), the system including one or more processors and a graphics processing unit (GPU), the GPU including a graphics security controller;
allocating by the graphics security controller a trusted key ID for a TD of the one or more TDs;
generating a non-secure version of address translation tables in the device memory, the address translation tables including an LMTT (Local Memory Translation Table) providing mapping of device physical addresses;
transitioning the TD to a secure state, including generating by the graphics security controller a secure version of the address translation tables, the secure version being an encrypted version of the address translation tables, and generating one or more encryption keys to provide access to the secure version of the address translation tables; and
receiving and processing a memory access request, wherein processing the memory access request includes:
upon determining that the memory access request is associated with the one or more TDs, accessing the secure version of the address translation tables using an encryption key of the one or more encryption keys, and
upon determining that the memory access request is not associated with the one or more TDs, accessing the non-secure version of the address translation tables;
wherein hardware of the GPU is to enforce usage of the secure version of the address translation tables for requests that are associated with the one or more TDs and the non-secure version of the address translation tables for requests that are not associated with the one or more TDs.