CPC G06F 12/0868 (2013.01) [G06F 3/065 (2013.01); G06F 3/068 (2013.01); G06F 3/0619 (2013.01); G06F 12/0811 (2013.01); G06F 12/0871 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/283 (2013.01); G06F 2212/311 (2013.01); G06F 2212/6046 (2013.01)] | 25 Claims |
1. A processor comprising:
a first register to store a first data;
decoder to decode a store instruction, the store instruction including a source data operand to identify the first register and a destination data operand to identify a first memory address, the first memory address associated with a first cache line in a remote cache which has sole ownership of the first cache line; and
execution circuitry to execute the decoded store instruction to generate a write transaction to replace at least a portion of a second data in the first cache line in the remote cache with the first data from the first register to produce an updated first cache line, wherein the remote cache is to retain sole ownership of the first cache line during the write transaction.
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