US 11,816,036 B2
Method and system for performing data movement operations with read snapshot and in place write update
Anil Vasudevan, Portland, OR (US); Venkata Krishnan, Ashland, MA (US); Andrew J. Herdrich, Hillsboro, OR (US); Ren Wang, Portland, OR (US); Robert G. Blankenship, Tacoma, WA (US); Vedaraman Geetha, Fremont, CA (US); Shrikant M. Shah, Chandler, AZ (US); Marshall A. Millier, Banks, OR (US); Raanan Sade, Haifa (IL); Binh Q. Pham, Hillsboro, OR (US); Olivier Serres, Hudson, MA (US); Chyi-Chang Miao, Sharon, MA (US); and Christopher B. Wilkerson, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 6, 2022, as Appl. No. 17/738,919.
Application 17/738,919 is a continuation of application No. 16/834,845, filed on Mar. 30, 2020, granted, now 11,327,894.
Application 16/834,845 is a continuation of application No. 15/640,060, filed on Jun. 30, 2017, granted, now 10,606,755, issued on Mar. 31, 2020.
Prior Publication US 2022/0261351 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0868 (2016.01); G06F 12/0897 (2016.01); G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 12/0868 (2013.01) [G06F 3/065 (2013.01); G06F 3/068 (2013.01); G06F 3/0619 (2013.01); G06F 12/0811 (2013.01); G06F 12/0871 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/283 (2013.01); G06F 2212/311 (2013.01); G06F 2212/6046 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A processor comprising:
a first register to store a first data;
decoder to decode a store instruction, the store instruction including a source data operand to identify the first register and a destination data operand to identify a first memory address, the first memory address associated with a first cache line in a remote cache which has sole ownership of the first cache line; and
execution circuitry to execute the decoded store instruction to generate a write transaction to replace at least a portion of a second data in the first cache line in the remote cache with the first data from the first register to produce an updated first cache line, wherein the remote cache is to retain sole ownership of the first cache line during the write transaction.