| CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 17/16 (2013.01); H03M 13/1575 (2013.01)] | 20 Claims |
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1. A memory controller configured to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, the memory controller comprising:
an error correction code (ECC) engine;
a central processing unit (CPU) configured to control the ECC engine; and
an error managing circuit,
wherein the ECC engine is configured to:
during a read operation, perform an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome associated with a correctable error in a user data set included in the read codeword set;
correct the correctable error based on the first syndrome and the second syndrome; and
provide the second syndrome to the error managing circuit, and
wherein the error managing circuit is configured to:
accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes;
store the plurality of second syndromes;
compare the plurality of second syndromes with an error pattern set; and
predict an occurrence of an uncorrectable error associated with the correctable error in a memory region of the plurality of data chips based on the comparison.
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