US 11,815,976 B2
Bandwidth based power management for peripheral component interconnect express devices
Thiyagarajan Selvam, San Diego, CA (US); Dilip Venkateswaran Murali, San Diego, CA (US); Murali Krishna, San Diego, CA (US); Sujeev Dias, San Marcos, CA (US); and Tony Truong, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 13, 2020, as Appl. No. 15/931,409.
Claims priority of provisional application 62/852,925, filed on May 24, 2019.
Claims priority of provisional application 62/851,633, filed on May 22, 2019.
Prior Publication US 2020/0371579 A1, Nov. 26, 2020
Int. Cl. G06F 1/3234 (2019.01); G06F 13/42 (2006.01)
CPC G06F 1/3253 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 34 Claims
OG exemplary drawing
 
1. A system comprising:
a first chip that includes:
a host device;
a host controller;
a first peripheral component interconnect express (PCIe) interface circuit; and
a host system bus interface configured to couple the host device, the host controller and the first PCIe interface circuit;
a second chip that includes:
multiple clients;
an endpoint device controller that is configured to control the multiple clients;
a second PCIe interface circuit; and
a client system bus interface configured to couple the multiple clients, the endpoint device controller and the second PCIe interface circuit; and
a link that couples the first PCIe interface circuit with the second PCIe interface circuit,
wherein the second PCIe interface circuit includes a serializer configured to serialize parallel transmit data received over the client system bus interface from the multiple clients, the parallel transmit data being generated for transmission over the link,
and wherein the endpoint device controller is configured to:
receive multiple bandwidth requests over the client system bus interface from the multiple clients;
aggregate the multiple bandwidth requests into an aggregate bandwidth request;
determine at least one of a link speed and a link width for the link based on the aggregate bandwidth request including determining when a change in the link speed or the link width is needed based on the aggregate bandwidth request; and
send a speed change request to the host device via the second PCIe interface circuit, the link, and the first PCIe interface circuit after determining the at least one of the link speed and the link width.