US 11,815,769 B2
Display device
Ryosuke Yuminami, Sakai (JP); Masakazu Miyamoto, Sakai (JP); Masahiro Yoshida, Sakai (JP); Masayuki Takashima, Sakai (JP); and Toshiaki Fujihara, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
Filed on Nov. 22, 2022, as Appl. No. 17/991,868.
Application 17/991,868 is a continuation of application No. 17/238,256, filed on Apr. 23, 2021, granted, now 11,513,403.
Application 17/238,256 is a continuation of application No. 16/459,799, filed on Jul. 2, 2019, granted, now 10,989,967, issued on Apr. 27, 2021.
Application 16/459,799 is a continuation of application No. 14/785,388, granted, now 10,394,094, issued on Aug. 27, 2019, previously published as PCT/JP2014/054809, filed on Feb. 27, 2014.
Claims priority of application No. 2013-092836 (JP), filed on Apr. 25, 2013.
Prior Publication US 2023/0080375 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/1345 (2006.01); G02F 1/1335 (2006.01); G02F 1/1337 (2006.01); G02F 1/1339 (2006.01); G02F 1/1333 (2006.01)
CPC G02F 1/13452 (2013.01) [G02F 1/1337 (2013.01); G02F 1/1339 (2013.01); G02F 1/1345 (2013.01); G02F 1/133512 (2013.01); G02F 1/133388 (2021.01)] 22 Claims
OG exemplary drawing
 
1. A display device comprising:
a display area where images are displayed;
a non-display area that is outside the display area;
substrates each including the display area and the non-display area; and
a liquid crystal layer sandwiched between the substrates;
one of the substrates including:
lines in the display area;
connection lines at intervals in the non-display area;
at least two groups of terminals at intervals in the non-display area;
at least two groups of the connection lines connecting the at least two groups of the terminals and the lines, respectively;
the at least two groups of connection lines including at least two narrow line portions, respectively;
the at least two narrow line portions respectively spreading outwardly with increasing distance from the at least two groups of the terminals;
a wide line portion between the at least two narrow line portions;
pixel electrodes provided in the display area;
an insulation film that covers the wide line portion and the at least two narrow line portions; and
contact holes formed in a portion of the insulation film; and
another one of the substrates including:
a light blocking portion overlapped with the connection lines and the wide line portion in the non-display area, wherein
the wide line portion includes divided lines that are defined by empty portions and are arranged at intervals,
the wide line portion includes a short-circuit portion to short-circuit adjacent divided lines,
a common electrode that is opposite to the pixel electrodes, and
the wide line portion is connected to the common electrode via the contact holes at a portion where the light blocking portion is in the non-display area.