US 11,815,749 B2
Functional element housing package, and semiconductor device and LN modulator
Hiroyuki Nakamichi, Kirishima (JP); and Takayuki Shirasaki, Omihachiman (JP)
Assigned to Kyocera Corporation, Kyoto (JP)
Appl. No. 16/087,985
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Mar. 27, 2017, PCT No. PCT/JP2017/012386
§ 371(c)(1), (2) Date Aug. 7, 2020,
PCT Pub. No. WO2017/164418, PCT Pub. Date Sep. 28, 2017.
Claims priority of application No. 2016-061104 (JP), filed on Mar. 25, 2016.
Prior Publication US 2021/0208428 A1, Jul. 8, 2021
Int. Cl. G02F 1/03 (2006.01); H01L 23/055 (2006.01); H05K 1/18 (2006.01); G02F 1/055 (2006.01)
CPC G02F 1/0305 (2013.01) [H01L 23/055 (2013.01); H05K 1/18 (2013.01); H05K 1/189 (2013.01); G02F 1/055 (2013.01); H05K 2201/10121 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A functional element housing package, comprising:
a housing which houses a functional element;
a pin terminal disposed in an outer region of the housing; and
a wiring substrate comprising
a through hole for receiving the pin terminal,
a first metallic layer disposed around an opening of the through hole on a side of the wiring substrate which side is located close to the housing,
a second metallic layer disposed around an opening of the through hole on a side of the wiring substrate which side is opposed to the side located close to the housing, the second metallic layer being greater in area than the first metallic layer,
a connection wiring line connected to the first metallic layer or the second metallic layer, and
a solder which connects the pin terminal to each of the first metallic layer and the second metallic layer.