US 11,815,555 B2
Universal compactor architecture for testing circuits
Yingdi Liu, Wilsonville, OR (US); Nilanjan Mukherjee, Wilsonville, OR (US); Janusz Rajski, West Linn, OR (US); Grzegorz Mrugalski, Swarzedz (PL); Jerzy Tyszer, Poznan (PL); and Bartosz Wlodarczak, Swarzȩdz (PL)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Appl. No. 17/753,332
Filed by Siemens Industry Software Inc., Plano, TX (US)
PCT Filed Sep. 6, 2019, PCT No. PCT/US2019/049834
§ 371(c)(1), (2) Date Feb. 28, 2022,
PCT Pub. No. WO2021/045769, PCT Pub. Date Mar. 11, 2021.
Prior Publication US 2022/0308110 A1, Sep. 29, 2022
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/318533 (2013.01); G01R 31/318547 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a test response compactor configured to compact the test responses; and
scan gating devices inserted between outputs of the scan chains and inputs of the test response compactor, the scan gating devices dividing the scan chains into groups of scan chains, each of the scan gating devices receiving signals from outputs of one of the groups of scan chains and operating in either an enabled mode or a disenabled mode based on a first signal,
wherein a portion of a test response of a test pattern outputted from each scan chain coupled to a scan gating device operating in the enabled mode is either blocked, or not blocked, or blocked only at one or more cycles from reaching the test response compactor based on a particular bit of a second signal, at least a portion of the second signal being delivered bit-by-bit continuously when the test response is being shifted out, and
wherein another portion of the test response of the test pattern outputted from all scan chains in each of groups of scan chains coupled to scan gating devices operating in the disenabled mode are either blocked or not blocked from reaching the test response compactor based on a third signal.