US 11,815,486 B2
Ion sensitive field effect transistor (FET) with back-gate coupled reference electrode
Paul M. Solomon, Yorktown Heights, NY (US); and Sufi Zafar, Briarcliff Manor, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 18, 2021, as Appl. No. 17/151,371.
Application 17/151,371 is a division of application No. 15/299,762, filed on Oct. 21, 2016, granted, now 10,928,356.
Prior Publication US 2021/0181143 A1, Jun. 17, 2021
Int. Cl. G01N 27/414 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01)
CPC G01N 27/414 (2013.01) [H01L 29/1087 (2013.01); H01L 29/408 (2013.01); H01L 29/4238 (2013.01); H01L 29/42356 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An ion-sensitive field effect transistor apparatus, comprising:
a silicon on insulator substrate, in turn comprising a top silicon layer, a buried oxide insulator layer, and a bottom silicon layer a gate insulator spaced outwardly from said substrate, said gate insulator having an exposed outer surface configured for contact with a fluid analyte;
a device region formed in said top silicon layer intermediate said buried oxide insulator layer and said gate insulator;
a source region adjacent said device region;
a drain region adjacent said device region; and
a functionalized layer spaced outwardly of said bottom silicon layer away from said source, said drain, and said device region;
wherein said bottom silicon layer comprises a back gate reference voltage point.