US 11,814,126 B2
Driver alert system
Shuichi Katsui, Kanagawa (JP); and Takayuki Ikeda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/275,236
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Oct. 1, 2019, PCT No. PCT/IB2019/058317
§ 371(c)(1), (2) Date Mar. 11, 2021,
PCT Pub. No. WO2020/074998, PCT Pub. Date Apr. 16, 2020.
Claims priority of application No. 2018-192548 (JP), filed on Oct. 11, 2018.
Prior Publication US 2022/0041242 A1, Feb. 10, 2022
Int. Cl. B62J 50/21 (2020.01); G01S 15/04 (2006.01); G01S 15/931 (2020.01); G01S 7/526 (2006.01); H01L 27/06 (2006.01); H01L 29/786 (2006.01)
CPC B62J 50/21 (2020.02) [G01S 7/526 (2013.01); G01S 15/04 (2013.01); G01S 15/931 (2013.01); H01L 27/0688 (2013.01); H01L 29/7869 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A driver alert system comprising:
a first housing comprising:
a first transmission circuit transmitting a first ultrasonic wave;
a first receiving circuit receiving a second ultrasonic wave;
an arithmetic circuit detecting the presence or absence of an object from the second ultrasonic wave; and
a second transmission circuit transmitting a third ultrasonic wave on the basis of a signal obtained in the arithmetic circuit; and
a second housing comprising a second receiving circuit receiving the third ultrasonic wave,
wherein the arithmetic circuit comprises a first selection circuit selecting a potential based on the second ultrasonic wave at a different timing; a plurality of signal retention circuits retaining a potential based on the second ultrasonic wave; a second selection circuit selecting any one of the plurality of signal retention circuits; and a signal processing circuit to which a signal selected in and output from the second selection circuit is input;
wherein each of the plurality of signal retention circuits comprises a first transistor,
wherein the second ultrasonic wave is an ultrasonic wave obtained by reflection of the first ultrasonic wave,
wherein the first transistor comprises a semiconductor layer comprising an oxide semiconductor in a channel formation region,
wherein the second selection circuit selects the plurality of signal retention circuits at different timings to generate a signal obtained by delaying the second ultrasonic wave, and
wherein the third ultrasonic wave generated on the basis of the signal is transmitted to the second housing.