| US 7,450,680 B2 | ||
| Fractional-N divider configurable as a polynomial function for real-time PLL swept frequency applications | ||
| Wing J. Mar, Rohnert Park, Calif. (US) | ||
| Assigned to Agilent Technologies, Inc., Santa Clara, Calif. (US) | ||
| Filed on Oct. 19, 2006, as Appl. No. 11/550,860. | ||
| Prior Publication US 2008/0094144 A1, Apr. 24, 2008 | ||
| Int. Cl. H03K 21/00 (2006.01); H03K 23/00 (2006.01) | ||
| U.S. Cl. 377—47 [377/48] | 4 Claims |
| 1. A circuit comprising:
a reference clock generating a reference signal;
a phase accumulator generating a phase signal;
a frequency divider includes a sigma-delta modulator, receiving the reference signal and the phase signal, generating a frequency
divided signal, wherein the phase accumulator receives the frequency divided signal;
an incremental clock generating an incremental signal; and
a frequency accumulator, receiving the incremental signal, generating a correction signal, wherein the phase accumulator receives
the correction signal.
|