a plurality of memory elements disposed in columns;

word lines to which a select signal is applied to allow data to be input to and output from a predetermined one of said plurality of memory elements;

bit lines and inverted bit lines connected to said plurality of memory elements and input with signals having mutually inverted logical levels when data is to be written to the memory element selected by said select signal;

a signal generator circuit for generating an input signal for test;

a switch circuit for switching between a first state in which an input signal generated by said signal generator circuit is input to said bit line and a second state in which an input signal generated by said signal generator circuit is input to said inverted bit line;

a word line designating circuit for applying the select signal to said word line in such a manner that the memory element to which said input signal is input via said bit line or said inverted bit line is changed in a predetermined order, and

a detector circuit for detecting whether said input signal input via said bit line or said inverted bit line to said memory element selected by the select signal supplied from said word line designating circuit and an output signal output from said inverted bit line or said bit line in response to said input signal correspond to data having mutually inverted logical levels,

wherein while said switch circuit retains said first state, said word line designating circuit operates to input said input signal , and thereafter while said switch circuit retains said second state, said word line designating circuit operates to input said input signal.