| US 7,449,900 B2 | ||
| Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof | ||
| Yasuo Yamagishi, Kawasaki (Japan) | ||
| Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
| Filed on Jul. 14, 2006, as Appl. No. 11/486,054. | ||
| Application 11/486054 is a division of application No. 10/621445, filed on Jul. 18, 2003, granted, now 7,102,367. | ||
| Claims priority of application No. 2002-214476 (JP), filed on Jul. 23, 2002; application No. 2003-020663 (JP), filed on Jan. 29, 2003; and application No. 2003-270360 (JP), filed on Jul. 02, 2003. | ||
| Prior Publication US 2006/0255817 A1, Nov. 16, 2006 | ||
| Int. Cl. G01R 31/02 (2006.01) | ||
| U.S. Cl. 324—754 | 14 Claims |
| 1. A probe card for testing a semiconductor chip, comprising:
a first interconnection substrate;
a second interconnection substrate mounted on said first interconnection substrate in such a manner such that a gap is formed
between said first interconnection substrate and said second interconnection substrate;
a plurality of probes provided on said second interconnection substrate at a surface away from said first interconnection
substrate; and
a decoupling capacitor provided within said gap on said second interconnection substrate at a surface facing said first interconnection
substrate,
wherein said first interconnection substrate and said second interconnection substrate are connected by a pin grid array.
|