| US 7,449,407 B2 | ||
| Air gap for dual damascene applications | ||
| Water Lur, Taipei (Taiwan); David Lee, Hsin-chu (Taiwan); Kuang-Chih Wang, Taichung (Taiwan); and Ming-Sheng Yang, Hsin-chu (Taiwan) | ||
| Assigned to United Microelectronics Corporation, Hsin-Chu (Taiwan) | ||
| Filed on Nov. 15, 2002, as Appl. No. 10/295,719. | ||
| Prior Publication US 2004/0094821 A1, May 20, 2004 | ||
| Int. Cl. H01L 21/764 (2006.01); H01L 21/768 (2006.01) | ||
| U.S. Cl. 438—619 [257/E21.573; 257/E21.579; 257/E21.581] | 25 Claims |
| 1. A method for forming an air gap structure in an integrated circuit, the method comprising:
forming a device layer;
forming a dual damascene opening over the device layer including first and second patterned openings in at least one first
dielectric layer;
forming a dual damascene conductive pattern of conductive lines by filling the first and second patterned openings with at
least one conductive material;
forming a adjustable-depth trench between adjacent conductive lines in said dual damascene conductive pattern using the dual
damascene conductive structure as a hard mask; and
forming a second dielectric layer over the trench to encapsulate said trench and form at least one air gap therein.
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