| US 7,449,393 B2 | ||
| Method of manufacturing a semiconductor device with a shallow trench isolation structure | ||
| Kenji Saitou, Kanagawa (Japan); and Kenichi Hidaka, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kawasaki (Japan) | ||
| Filed on Mar. 25, 2005, as Appl. No. 11/90,839. | ||
| Claims priority of application No. 2004/101663 (JP), filed on Mar. 31, 2004. | ||
| Prior Publication US 2005/0221580 A1, Oct. 06, 2005 | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—435 [438/690; 438/692; 257/E21.546] | 21 Claims |
| 1. A method of manufacturing a semiconductor device with a shallow trench isolation structure, comprising:
forming trenches extending into a semiconductor substrate;
forming a first insulating film to fully fill the trenches and to cover a whole surface of the semiconductor substrate;
carrying out a first chemical mechanical polishing (CMP) to remove the first insulating film and any foreign substance that
prevents any of the trenches from being fully filled by the first insulating film such that the first insulating film is left
only in the trenches;
forming a second insulating film to fill a concave in said first insulating film caused by said foreign substance; and
carrying out a second CMP such that the second insulating film is left only in said concave.
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