CPC H10N 50/80 (2023.02) [H10B 51/30 (2023.02); H10B 61/00 (2023.02); H10B 63/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/881 (2023.02)] | 16 Claims |
1. A method, comprising:
forming a spacer structure above a memory state material of a memory cell, the spacer structure having a generally U-shaped configuration when viewed in a vertical cross-section;
forming at least one first layer of insulating material above the generally U-shaped spacer structure;
forming a contact opening in the at least one first layer of insulating material, whereby the contact opening exposes the generally U-shaped spacer structure;
performing an etching process through the contact opening on the generally U-shaped spacer structure so as to remove a portion of the generally U-shaped spacer structure and thereby form an internal sidewall spacer positioned above at least a portion of the memory state material, the internal sidewall spacer defining a spacer opening that exposes at least a portion of the memory state material; and
forming a conductive contact structure in the contact opening, the conductive contact structure comprising a conductive line portion and a conductive via portion, wherein the conductive via portion is formed in the spacer opening and wherein the conductive via portion contacts the memory state material.
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