US 11,812,668 B2
Pillar-based memory hardmask smoothing and stress reduction
Michael Rizzolo, Delmar, NY (US); Theodorus E. Standaert, Clifton Park, NY (US); Ashim Dutta, Clifton Park, NY (US); and Dominik Metzler, Clifton Park, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,027.
Application 17/552,027 is a division of application No. 16/697,452, filed on Nov. 27, 2019, granted, now 11,223,008.
Prior Publication US 2022/0109099 A1, Apr. 7, 2022
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10B 63/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02); H10N 70/026 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a base structure including a first contact of a memory device;
a memory pillar disposed on the base structure, including:
a conductive central core having a roughness; and
a conductive shell layer surrounding the conductive central core to reduce the roughness;
an encapsulation layer formed on the memory pillar; and
a second contact formed on the memory pillar and the encapsulation layer, wherein the memory pillar includes a cross-section having a parabolic shape.