US 11,812,619 B2
Resistive memory devices
Jinwoo Lee, Seoul (KR); Zhe Wu, Seoul (KR); Dongsung Choi, Hwaseong-si (KR); Chungman Kim, Suwon-si (KR); Seunggeun Yu, Seoul (KR); Jabin Lee, Hwaseong-si (KR); and Soyeon Choi, Gangjin-gun (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 12, 2021, as Appl. No. 17/227,852.
Claims priority of application No. 10-2020-0101397 (KR), filed on Aug. 12, 2020.
Prior Publication US 2022/0052116 A1, Feb. 17, 2022
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/84 (2023.02) [H10N 70/826 (2023.02); H10N 70/841 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A resistive memory device comprising:
a first conductive line extending in a first horizontal direction on a substrate;
a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction, intersecting with the first horizontal direction, on the substrate;
a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells comprising a selection device and a resistive memory pattern; and
a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction and comprising a top surface having a concave-convex shape;
wherein the bottom electrode is between the first conductive line and the selection device; and
wherein a width of the bottom electrode is less than a width of the selection device in the second horizontal direction.