US 11,812,618 B2
Nonvolatile memory device including ferroelectric layer having negative capacitance
Jae Gil Lee, Seoul (KR); Hyangkeun Yoo, Gyeonggi-do (KR); and Se Ho Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 25, 2022, as Appl. No. 17/872,838.
Application 17/872,838 is a division of application No. 16/821,186, filed on Mar. 17, 2020, granted, now 11,430,812.
Claims priority of application No. 10-2019-0093548 (KR), filed on Jul. 31, 2019.
Prior Publication US 2022/0359543 A1, Nov. 10, 2022
Int. Cl. H01L 21/00 (2006.01); H10B 51/30 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 51/30 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a substrate;
an electrode stack structure disposed on the substrate, wherein the electrode stack structure includes at least one gate electrode layer and at least one interlayer insulation layer alternatively stacked on the substrate;
a trench that penetrates the electrode stack structure and exposes sidewall surfaces of the gate electrode layer and the interlayer insulation layer;
an internal voltage amplification layer disposed to cover the interlayer insulation layer and the gate electrode layer along an inner surface of the trench, the internal voltage amplification layer being a ferroelectric layer having a negative capacitance;
a gate dielectric layer structure disposed on the internal voltage amplification layer, the gate dielectric layer structure having a positive capacitance; and
a channel layer disposed on the gate dielectric layer structure,
wherein the gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer,
wherein the nonvolatile memory device has an operation gate voltage corresponding to a polarization switching voltage of the internal voltage amplification layer,
wherein when the operation gate voltage is applied to the gate electrode layer, an internal voltage greater than the operation gate voltage is applied to the gate dielectric layer structure.