US 11,812,615 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Jul. 1, 2022, as Appl. No. 17/856,703.
Application 17/856,703 is a division of application No. 16/918,445, filed on Jul. 1, 2020, granted, now 11,411,022.
Claims priority of application No. 10-2020-0005632 (KR), filed on Jan. 15, 2020.
Prior Publication US 2022/0352202 A1, Nov. 3, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/67 (2006.01); H01L 21/02 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 29/06 (2006.01); G11C 8/14 (2006.01); H10B 41/20 (2023.01); H10B 41/30 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 21/02019 (2013.01); H01L 21/67063 (2013.01); H01L 23/5226 (2013.01); H01L 29/0653 (2013.01); H10B 41/20 (2023.02); H10B 41/30 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2221/1063 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a first select gate layer having a bottom surface facing a first substrate;
forming a stack structure, wherein the stack structure includes a second select gate layer overlapping with the first select gate layer and interlayer insulating layers and conductive patterns, which are alternately stacked on the second select gate layer;
removing the first substrate; and
etching the first select gate layer and the second select gate layer from the bottom surface of the first select gate layer to form a slit penetrating the first select gate layer and the second select gate layer.