US 11,812,613 B2
Semiconductor memory device including select transistor with low dielectric core insulating layer and method of manufacturing the same
Dae Hwan Yun, Icheon-si (KR); and Gil Bok Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 24, 2021, as Appl. No. 17/211,460.
Claims priority of application No. 10-2020-0125019 (KR), filed on Sep. 25, 2020.
Prior Publication US 2022/0102371 A1, Mar. 31, 2022
Int. Cl. H10B 43/35 (2023.01); H10B 43/27 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and
a plurality of channel structures passing through the stack in a vertical direction,
wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and
wherein a dielectric constant of a first region of the core insulating layer, which corresponds to a source select transistor or a drain select transistor, is lower than a dielectric constant of a second region of the core insulating layer which corresponds to memory cells.