US 11,812,612 B2
Semiconductor device and manufacturing method of semiconductor device
Kun Young Lee, Icheon-si (KR); and Dong Hyoub Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 12, 2021, as Appl. No. 17/147,260.
Claims priority of application No. 10-2020-0078380 (KR), filed on Jun. 26, 2020.
Prior Publication US 2021/0408036 A1, Dec. 30, 2021
Int. Cl. H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 63/00 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stacked structure with conductive layers and insulating layers that are stacked alternately with each other in a stacking direction;
an insulating pillar passing through the stacked structure;
a first channel pattern surrounding a sidewall of the insulating pillar;
a second channel pattern surrounding the sidewall of the insulating pillar;
first insulators located between the first channel pattern and the second channel pattern; and
a memory layer surrounding the first channel pattern, the second channel pattern, and each of the first insulators, the memory layer with a first opening that is located between the first channel pattern and the second channel pattern,
wherein the first insulators are separated from each other in the stacking direction.