US 11,812,608 B2
Semiconductor device and manufacturing method thereof
Tsun-Kai Tsao, Tainan (TW); Hung-Ling Shih, Tainan (TW); Po-Wei Liu, Tainan (TW); Shun-Shing Yang, Tainan (TW); Wen-Tuo Huang, Tainan (TW); Yong-Shiuan Tsair, Tainan (TW); and ShihKuang Yang, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 10, 2021, as Appl. No. 17/316,278.
Application 15/914,485 is a division of application No. 15/209,370, filed on Jul. 13, 2016, granted, now 9,929,167, issued on Mar. 27, 2018.
Application 17/316,278 is a continuation of application No. 16/370,736, filed on Mar. 29, 2019, granted, now 11,004,858, issued on May 11, 2021.
Application 16/370,736 is a continuation of application No. 15/914,485, filed on Mar. 7, 2018, granted, now 10,269,818, issued on Apr. 23, 2019.
Prior Publication US 2021/0280593 A1, Sep. 9, 2021
Int. Cl. H10B 41/41 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/30 (2023.01); H01L 21/3105 (2006.01)
CPC H10B 41/41 (2023.02) [H01L 21/31056 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
18. A semiconductor device including a non-volatile memory and a logic circuit, wherein:
the non-volatile memory includes:
a shallow trench isolation (STI) structure;
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
first sidewalls made of a first dielectric material and disposed over opposing side faces of the stacked structure;
an erase gate line; and
a word line,
the logic circuit includes a field effect transistor comprising a gate electrode, and
an upper surface of the floating gate has a first portion and a second portion higher than the first portion, and a top of the second portion is higher than a top surface of the STI structure, and the first insulating layer is disposed below the top surface of the STI structure.