CPC H10B 41/41 (2023.02) [H01L 21/31056 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H10B 41/30 (2023.02)] | 20 Claims |
18. A semiconductor device including a non-volatile memory and a logic circuit, wherein:
the non-volatile memory includes:
a shallow trench isolation (STI) structure;
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
first sidewalls made of a first dielectric material and disposed over opposing side faces of the stacked structure;
an erase gate line; and
a word line,
the logic circuit includes a field effect transistor comprising a gate electrode, and
an upper surface of the floating gate has a first portion and a second portion higher than the first portion, and a top of the second portion is higher than a top surface of the STI structure, and the first insulating layer is disposed below the top surface of the STI structure.
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