US 11,812,600 B2
Vertical memory cell with self-aligned thin film transistor
Seung Hoon Sung, Portland, OR (US); Charles C. Kuo, Hillsboro, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); and Jack Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2019, as Appl. No. 16/452,099.
Prior Publication US 2020/0411528 A1, Dec. 31, 2020
Int. Cl. H10B 12/00 (2023.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H10B 12/05 (2023.02) [H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H10B 12/036 (2023.02); H10B 12/33 (2023.02); H10B 12/482 (2023.02)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
one or more layers of insulating material defining a vertical bore with a first portion and a second portion, wherein sidewalls of the first and the second portions are colinear;
a capacitor structure in the first portion of the vertical bore, the capacitor structure including a first electrode, a second electrode, and a first dielectric between the first electrode and the second electrode, wherein the first electrode, the second electrode and the first dielectric are in the first portion of the vertical bore, wherein the first electrode has an uppermost surface, and wherein the first dielectric is on and covers the uppermost surface of the first electrode;
a transistor structure in the second portion of the vertical bore, the transistor structure including a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the third electrode and in contact with the second electrode, and a second dielectric between the semiconductor material and the insulating material; and
a fourth electrode wrapped around at least a portion of the transistor structure, such that the second dielectric is between the semiconductor material and the fourth electrode;
wherein sidewalls of the capacitor structure and the transistor structure are colinear.