US 11,811,903 B2
Distributed dynamic architecture for error correction
Rita H. Wouhaybi, Portland, OR (US); Robert Chavez, Phoenix, AZ (US); Mark Yarvis, Portland, OR (US); John Vicente, Roseville, CA (US); and Kirk Smith, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 23, 2022, as Appl. No. 17/679,003.
Application 17/679,003 is a continuation of application No. 17/120,512, filed on Dec. 14, 2020, granted, now 11,265,402.
Application 17/120,512 is a continuation of application No. 16/147,168, filed on Sep. 28, 2018, granted, now 10,868,895.
Claims priority of provisional application 62/612,092, filed on Dec. 29, 2017.
Claims priority of provisional application 62/587,227, filed on Nov. 16, 2017.
Prior Publication US 2022/0329676 A1, Oct. 13, 2022
Int. Cl. H04L 69/40 (2022.01); H04L 67/10 (2022.01); G05B 19/042 (2006.01); G05B 19/05 (2006.01); G05B 19/418 (2006.01); H04L 41/082 (2022.01); H04L 41/084 (2022.01); H04L 67/04 (2022.01); H04L 67/104 (2022.01); H04L 67/12 (2022.01); H04L 67/125 (2022.01); H04L 67/00 (2022.01); G06F 8/65 (2018.01); G06F 11/20 (2006.01); H04L 67/565 (2022.01); H04L 41/0668 (2022.01)
CPC H04L 69/40 (2013.01) [G05B 19/042 (2013.01); G05B 19/054 (2013.01); G05B 19/41835 (2013.01); G06F 8/65 (2013.01); G06F 11/2023 (2013.01); G06F 11/2033 (2013.01); H04L 41/0668 (2013.01); H04L 41/082 (2013.01); H04L 41/0846 (2013.01); H04L 67/04 (2013.01); H04L 67/10 (2013.01); H04L 67/1048 (2013.01); H04L 67/1051 (2013.01); H04L 67/12 (2013.01); H04L 67/125 (2013.01); H04L 67/34 (2013.01); H04L 67/565 (2022.05); G05B 2219/1105 (2013.01); G05B 2219/1214 (2013.01); G05B 2219/32043 (2013.01); G05B 2219/33112 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01); G06F 2201/85 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An orchestrated system of distributed nodes running an application, the orchestrated system comprising:
a managing node executing a first software component with a first output; and
a backup node executing a second software component, the second software component using the first output as an input, and providing a second output to a third software component executing on a dependent node;
wherein, in response to detection of a failure of the managing node, the backup node is configured to bypass the managing node by using input state information stored at the backup node and output state information stored at the backup node to run the first software component at the backup node.