US 11,811,685 B1
Selective packet processing including a run-to-completion packet processing data plane
Kiran K N, Bangalore (IN); Przemyslaw Krzysztof Grygiel, Gniezno (PL); and Damian Szeluga, Vienna (AT)
Assigned to Juniper Networks, Inc., Sunnyvale, CA (US)
Filed by Juniper Networks, Inc., Sunnyvale, CA (US)
Filed on Jul. 18, 2022, as Appl. No. 17/813,226.
Application 17/813,226 is a continuation of application No. 17/301,367, filed on Mar. 31, 2021, granted, now 11,394,663.
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/00 (2022.01); H04L 47/625 (2022.01); H04L 47/56 (2022.01)
CPC H04L 49/3063 (2013.01) [H04L 47/56 (2013.01); H04L 47/6255 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of logical cores, each of the plurality of logical cores comprising a central processing unit (CPU) core or hardware thread;
a physical network interface configured to receive network packets; and
a virtual router executable by the plurality of logical cores, the virtual router implementing a plurality of packet processing modes, the packet processing modes including a run-to-completion mode, the virtual router configured to:
in response to a determination that the virtual router is to operate in the run-to-completion mode, configure a logical core of the plurality of logical cores to:
read a network packet received by the physical network interface,
process the network packet to determine a destination virtual device for the network packet, the destination virtual device having a plurality of interface queues, and
insert the network packet into an interface queue, of the plurality of interface queues, to which the logical core is assigned.