CPC H03L 7/093 (2013.01) [G06F 1/022 (2013.01); G06F 1/0321 (2013.01); G06F 1/08 (2013.01); H03L 7/08 (2013.01); H03L 2207/50 (2013.01); H04L 2027/0065 (2013.01); H04L 2027/0073 (2013.01)] | 15 Claims |
1. A direct digital synthesizer (DDS) circuit, comprising:
a first input to receive a first fixed frequency clock signal having a first frequency;
a second input to receive a second fixed frequency clock signal having a second frequency that is lower than the first frequency;
an output to provide an output frequency, the output frequency based at least in part on a frequency control word; and
a frequency correction circuit having a first input to receive the first fixed frequency clock signal, a second input to receive the second fixed frequency clock signal, and a third input to receive the frequency control word, and an output to provide a frequency error of the first fixed frequency clock signal, the frequency error determined using a ratio of the first fixed frequency clock signal and the second fixed frequency clock signal and the frequency control word;
wherein the frequency correction circuit is configured to correct a frequency error and/or frequency wander of the first fixed frequency clock signal by summing an accumulated phase to the first fixed frequency clock, wherein the frequency error and/or frequency wander is determined based on a known fixed period of the second fixed frequency clock signal.
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