US 11,811,411 B2
Glitch filter system
Abhijit Kumar Das, Plano, TX (US); and Ryan Alexander Smith, Lucas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on May 2, 2022, as Appl. No. 17/734,227.
Application 17/734,227 is a continuation of application No. 17/101,511, filed on Nov. 23, 2020, granted, now 11,323,106.
Prior Publication US 2022/0263500 A1, Aug. 18, 2022
Int. Cl. H03K 5/1252 (2006.01); H03K 17/16 (2006.01)
CPC H03K 5/1252 (2013.01) [H03K 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A glitch filter system comprising:
an input stage including a first output and a second output, the input stage including a delay element having an input and an output, the input being coupled to the first output of the input stage and the output being coupled to the second output of the input stage;
a C-element including a first input coupled to the first output of the input stage, wherein the C-element further includes a second input coupled to the second output of the input stage, and wherein the C-element further includes an output; and
an output latch including:
a first P-type transistor including a gate coupled to the second output of the input stage, wherein the first P-type transistor further includes a drain coupled to the output of the C-element, and wherein the first P-type transistor further includes a source;
a second P-type transistor including a gate coupled to the first output of the input stage, wherein the second P-type transistor further includes a drain coupled to the output of the C-element, and wherein the second P-type transistor further includes a source coupled to the source of the first P-type transistor;
a first N-type transistor including a gate coupled to the second output of the input stage, wherein the first N-type transistor further includes a drain coupled to the output of the C-element, and wherein the first N-type transistor further includes a source; and
a second N-type transistor including a gate coupled to the first output of the input stage, wherein the second N-type transistor further includes a drain coupled to the output of the C-element, and wherein the second N-type transistor further includes a source coupled to the source of the first N-type transistor.