US 11,811,364 B2
Clock integrated circuit including heterogeneous oscillators and apparatus including the clock integrated circuit
Jaehong Jung, Bucheon-si (KR); Seunghyun Oh, Seoul (KR); Jinhyeon Lee, Hwaseong-si (KR); Gihyeok Ha, Seoul (KR); Seungjin Kim, Yongin-si (KR); Joomyoung Kim, Hwaseong-si (KR); Yelim Youn, Hwaseong-si (KR); and Jaehoon Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 21, 2022, as Appl. No. 17/845,378.
Claims priority of application No. 10-2021-0081039 (KR), filed on Jun. 22, 2021; and application No. 10-2021-0126725 (KR), filed on Sep. 24, 2021.
Prior Publication US 2022/0407459 A1, Dec. 22, 2022
Int. Cl. H03B 5/32 (2006.01); G06F 1/06 (2006.01); H03B 5/04 (2006.01); H03B 5/20 (2006.01)
CPC H03B 5/32 (2013.01) [G06F 1/06 (2013.01); H03B 5/04 (2013.01); H03B 5/20 (2013.01); H03B 2200/0082 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock integrated circuit comprising:
a first clock generator which comprises a crystal oscillator and is configured to use the crystal oscillator to generate a first clock signal; and
a second clock generator which comprises a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to:
generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator;
perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and
perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.