CPC H01L 27/1461 (2013.01) [H01L 27/14607 (2013.01); H04N 25/75 (2023.01); H04N 25/771 (2023.01); H04N 25/772 (2023.01); H04N 25/79 (2023.01)] | 49 Claims |
1. A circuit comprising:
a first circuit area including a first group including a plurality of analog-to-digital (AD) conversion units configured to convert an analog signal to a digital signal, and a first memory group including a plurality of memories configured to hold the digital signal output from the first group;
a second circuit area including a second group including a plurality of AD conversion units configured to convert an analog signal to a digital signal, and a second memory group including a plurality of memories configured to hold the digital signal output from the second group; and
a counter configured to output a count signal to both of the plurality of AD conversion units in the first group and the plurality of AD conversion units in the second group,
wherein the counter is arranged between the first circuit area and the second circuit area.
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