US 11,810,858 B2
Semiconductor device including transistor with doped oxide semiconductor and method for manufacturing the semiconductor device
Junichi Koezuka, Tochigi (JP); Toshimitsu Obonai, Tochigi (JP); Masami Jintyou, Tochigi (JP); and Daisuke Kurosaki, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 26, 2022, as Appl. No. 17/729,306.
Application 17/729,306 is a continuation of application No. 16/957,159, granted, now 11,322,442, previously published as PCT/IB2018/060299, filed on Dec. 19, 2018.
Claims priority of application No. 2018-000501 (JP), filed on Jan. 5, 2018; and application No. 2018-021912 (JP), filed on Feb. 9, 2018.
Prior Publication US 2022/0310517 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/263 (2006.01); H01L 21/265 (2006.01)
CPC H01L 23/5329 (2013.01) [H01L 21/02129 (2013.01); H01L 21/265 (2013.01); H01L 21/2636 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first insulating layer;
a semiconductor layer over and in contact with the first insulating layer;
a second insulating layer over the semiconductor layer; and
a first conductive layer over the first insulating layer,
wherein the second insulating layer is in contact with a top surface of the semiconductor layer and a side surface of the semiconductor layer,
wherein the second insulating layer includes a portion in contact with the first insulating layer in a region not overlapping with the semiconductor layer,
wherein the first conductive layer includes a portion overlapping with the semiconductor layer,
wherein the semiconductor layer includes a metal oxide,
wherein the first insulating layer includes an oxide,
wherein the second insulating layer includes an oxide,
wherein the semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer,
wherein the second insulating layer includes a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer,
wherein the first insulating layer includes a fifth region not overlapping with the semiconductor layer and a sixth region overlapping with the semiconductor layer,
wherein the second region, the fourth region, the fifth region, and the sixth region contain a first element,
wherein the first element is phosphorus, boron, magnesium, aluminum, or silicon, and
wherein the fifth region includes a region with a higher concentration of the first element than the sixth region.