US 11,810,857 B2
Via for semiconductor device and method
Chia-Pang Kuo, Taoyuan (TW); Chih-Yi Chang, New Taipei (TW); Ming-Hsiao Hsieh, Hsinchu (TW); Wei-Hsiang Chan, Hsinchu (TW); Ya-Lien Lee, Baoshan Township (TW); Chien Chung Huang, Taichung (TW); Chun-Chieh Lin, Taichung (TW); and Hung-Wen Su, Jhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 25, 2020, as Appl. No. 17/001,917.
Prior Publication US 2022/0068826 A1, Mar. 3, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/76804 (2013.01); H01L 21/76846 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a first conductive feature in a first dielectric layer;
a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature comprises:
a metal adhesion layer over and physically contacting the first conductive feature;
a barrier layer extending along sidewalls of the second dielectric layer, wherein the barrier layer and the metal adhesion layer are different materials; and
a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends laterally between an overlying portion of the barrier layer and an underlying portion of the metal adhesion layer, wherein a sidewall of the portion of the conductive filling material and a sidewall of the underlying portion of the metal adhesion layer are coplanar.