US 11,810,851 B2
Semiconductor device and method for manufacturing the same
Hitoshi Okano, Kanagawa (JP); and Hiroyuki Kawashima, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Feb. 28, 2022, as Appl. No. 17/682,230.
Application 17/682,230 is a continuation of application No. 16/772,263, granted, now 11,296,020, previously published as PCT/JP2018/045035, filed on Dec. 7, 2018.
Claims priority of application No. 2017-244941 (JP), filed on Dec. 21, 2017.
Prior Publication US 2022/0302020 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 21/76843 (2013.01); H01L 23/528 (2013.01); H01L 28/60 (2013.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor substrate;
a first multilayer wiring layer formed on the first semiconductor substrate, wherein the first multilayer wiring layer includes a plurality of insulating layers;
a second semiconductor substrate;
a second multilayer wiring layer formed on the second semiconductor substrate, wherein the first multilayer wiring layer is bonded to the second multilayer wiring layer at a junction plane; and
a capacitive element, wherein the capacitive element includes a first electrode at least partially formed in first and second insulating layers of the first multilayer wiring layer, and a second electrode at least partially formed in the first and second insulating layers of the first multilayer wiring layer.