US 11,810,814 B2
Vertical semiconductor device and method for fabricating the same
Jong-Hoon Kim, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Jun. 23, 2021, as Appl. No. 17/356,226.
Application 17/356,226 is a continuation of application No. 16/683,132, filed on Nov. 13, 2019, granted, now 11,075,111.
Claims priority of application No. 10-2019-0091072 (KR), filed on Jul. 26, 2019.
Prior Publication US 2021/0320031 A1, Oct. 14, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 21/76802 (2013.01) [H01L 21/76877 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A vertical semiconductor device comprising:
a substrate including a memory cell region and an alignment key region;
a memory cell stack in which dielectric layers and gate electrodes are alternately stacked in the memory cell region;
a dummy stack formed in the alignment key region;
a lower channel structure that penetrates a lower portion of the memory cell stack;
an upper channel structure that penetrates an upper portion of the memory cell stack and is located on the lower channel structure;
a lower stepped alignment key having a trench shape and disposed in a lower portion of the dummy stack; and
an upper stepped alignment key disposed in an upper portion of the dummy stack and caused by the lower stepped alignment key.
 
11. A semiconductor device comprising:
a substrate including an alignment key region;
a dummy stack formed in the alignment key region;
a lower stepped alignment key having a trench shape and disposed in a lower portion of the dummy stack; and
an upper stepped alignment key disposed in an upper portion of the dummy stack and caused by the lower stepped alignment key.