US 11,810,747 B2
Wafer scale enhanced gain electron bombarded CMOS imager
Dan W. Chilcott, Buchanan, VA (US); Arlynn W. Smith, Blue Ridge, VA (US); and John B. Hammond, Roanoke, VA (US)
Assigned to Elbit Systems of America, LLC, Fort Worth, TX (US)
Filed by Elbit Systems of America, LLC, Fort Worth, TX (US)
Filed on Jul. 15, 2021, as Appl. No. 17/377,065.
Claims priority of provisional application 63/058,256, filed on Jul. 29, 2020.
Prior Publication US 2022/0037106 A1, Feb. 3, 2022
Int. Cl. H01J 31/26 (2006.01); H01J 29/04 (2006.01); H01J 29/08 (2006.01)
CPC H01J 31/26 (2013.01) [H01J 29/04 (2013.01); H01J 29/085 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An image intensifier apparatus, comprising:
a photocathode wafer comprising a plurality of photocathode regions;
an interconnect wafer comprising a plurality of electrically separate sets of conductive traces formed in or upon the interconnect wafer;
a plurality of imager anodes integrated among or bonded to corresponding electrically separate sets of conductive traces;
an insulative spacer wafer with openings therein aligned over the imager anodes and between the interconnect wafer and the photocathode wafer; and
gaps within each space of a plurality of spaces formed between each imager anode of the plurality of imager anodes and each of the respective plurality of photocathodes through which the plurality of spaces are simultaneously evacuated to concurrently form a plurality of image intensifiers thereafter diced to form the image intensifier apparatus.