CPC G11C 16/26 (2013.01) [G11C 29/38 (2013.01); G11C 16/0483 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a solid-state memory comprising non-individually erasable memory cells;
a grouping circuit configured to arrange the memory cells into calibration groups, each memory cell in each respective calibration group using a common set of read voltages to sense programmed states of the respective memory cells; and
a tracking circuit configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group;
the grouping circuit further configured to reassign a set of memory cells comprising less than all of the memory cells of a first calibration group into a different, second calibration group in response to the at least one measured read parameter, the reassigned set of memory cells in the second group retaining the programmed states thereof without an intervening garbage collection operation upon the reassigned set of memory cells.
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