CPC G11C 16/26 (2013.01) [G06F 12/0246 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 16/0483 (2013.01)] | 18 Claims |
1. An operating method of a controller for controlling a semiconductor memory device including a plurality of memory cells, the method comprising:
generating program data to be stored in a selected page of the semiconductor memory device; and
controlling the semiconductor memory device to program the program data in the selected page,
wherein a threshold voltage of a memory cell located on a predetermined column maintains an erase state after program operation is complete, according to bit data at a predetermined position corresponding to the predetermined column in the program data.
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