US 11,810,621 B2
Memory sub-system sanitization
Eric N. Lee, San Jose, CA (US); Robert W. Strong, Folsom, CA (US); William Akin, Morgan Hill, CA (US); and Jeremy Binfet, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 27, 2021, as Appl. No. 17/458,795.
Prior Publication US 2023/0062226 A1, Mar. 2, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/16 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device;
increasing a source line voltage for a plurality of memory blocks of the memory device to a sanitization voltage; and
applying the sanitization voltage to the plurality of memory blocks of the memory device, wherein the sanitization voltage is greater than an erase voltage of the plurality of memory blocks.