US 11,810,620 B2
Semiconductor storage device
Hiroyuki Takenaka, Kamakura Kanagawa (JP); Akihiko Chiba, Yokohama Kanagawa (JP); Teppei Higashitsuji, Fujisawa Kanagawa (JP); Kiyofumi Sakurai, Yokohama Kanagawa (JP); Hiroaki Nakasa, Yokohama Kanagawa (JP); and Youichi Magome, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 26, 2021, as Appl. No. 17/458,067.
Claims priority of application No. 2021-015362 (JP), filed on Feb. 2, 2021.
Prior Publication US 2022/0246196 A1, Aug. 4, 2022
Int. Cl. G11C 8/12 (2006.01); G11C 16/14 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 5/06 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a first semiconductor substrate having a first active region;
a second semiconductor substrate having a second active region;
a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate;
a first word line electrically connected to a gate of the first memory cell;
a second word line electrically connected to a gate of the second memory cell;
a first transistor that is provided on the first semiconductor substrate and has a channel region thereof in the first active region, the first transistor having a first source and a first drain that are electrically connected between the first word line and a first wiring, the first transistor configured to control supply of a voltage from the first wiring to the gate of the first memory cell through the first word line; and
a second transistor that is provided on the second semiconductor substrate and has a channel region thereof in the second active region, the second transistor having a second source and a second drain that are electrically connected between the second word line and a second wiring, the second transistor configured to control supply of a voltage from the second wiring to the gate of the second memory cell through the second word line.