US 11,810,516 B2
Foveated display
Cheng Chen, San Jose, CA (US); Jason C. Sauers, Sunnyvale, CA (US); Fletcher R. Rothkopf, Los Altos, CA (US); David W. Lum, Cupertino, CA (US); Chun-Yao Huang, San Jose, CA (US); Enkhamgalan Dorjgotov, Mountain View, CA (US); Graham B. Myhre, Campbell, CA (US); Bennett S. Wilburn, Saratoga, CA (US); Paolo Sacchetto, Cupertino, CA (US); Shih Chang Chang, Cupertino, CA (US); Wonjae Choi, San Jose, CA (US); and Cheuk Chi Lo, Belmont, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 15, 2021, as Appl. No. 17/150,818.
Application 17/150,818 is a continuation of application No. 16/323,751, granted, now 10,930,219, previously published as PCT/US2017/046761, filed on Aug. 14, 2017.
Claims priority of provisional application 62/375,201, filed on Aug. 15, 2016.
Prior Publication US 2021/0142736 A1, May 13, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G09G 3/3225 (2016.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/20 (2013.01); G09G 3/3225 (2013.01); G09G 3/3275 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0218 (2013.01); G09G 2310/0221 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2340/0407 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
at least one lens;
an array of pixels configured to produce light that passes through the lens;
data lines;
data line driver circuitry configured to supply data signals to the pixels over the data lines with a dynamically adjustable resolution, wherein the data line driver circuitry includes an adjustable shift register, wherein the adjustable shift register includes a plurality of register blocks, and wherein each one of the plurality of register blocks includes a plurality of individual registers interconnected by multiplexer circuitry;
gate lines coupled to the pixels; and
gate line driver circuitry configured to supply gate line signals to the pixels over the gate lines with a dynamically adjustable resolution.