US 11,810,222 B2
Dedicated hardware unit to offload blending of values from memory
Prasoonkumar Surti, Folsom, CA (US); Larry Seiler, Boylston, MA (US); and Adam Z. Leibel, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 8, 2021, as Appl. No. 17/521,009.
Application 17/521,009 is a continuation of application No. 14/561,711, filed on Dec. 5, 2014, granted, now 11,170,460.
Prior Publication US 2022/0138894 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06T 15/00 (2011.01)
CPC G06T 1/20 (2013.01) [G06T 15/005 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a host processor including a shader compiler to generate a pixel shader;
shader bypass hardware separate from a graphics processor pipeline to bypass the graphics processor pipeline, the shader bypass hardware comprising logic, the logic to:
receive the pixel shader when one or more of the pixel shader or a render target satisfy a simplicity condition;
send one or more data read requests of the pixel shader to a sampler;
perform one or more fixed-function mathematical operations on the sampled data; and
write an output of the pixel shader to the render target,
wherein the simplicity condition includes a precision level of the render target being below a predetermined precision threshold.